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Altera_Forum's avatar
Altera_Forum
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15 years ago

Stratix IV DDR3 memory controller with Unify : simulation not working

Hello. I have a problem using DDR3 memory controller with Unify on Stratix IV. I use modelsim SE 6.5d or 10.0. My problem is that the controller is not working both with my design and Al...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

I run the simulation during 5 ms with the skip calibration enabled.

I also check the local_init_done. It os used as a enable for my application on the Avalon interface. It is because I never see my application running that I worried about the DDR3 interface.

I use the controller as a stand alone without SOPC builder.

I wonder why the DDR restn signal is still active after a so long time. The calibration can not be done if the DDR device is in reset state !?!

I feel my problem come from warning. These mismatched connexions seem not normal for me, as the non-loading of the hex file for the sequencer.

But I don't find how to solve them.

Does anyone experienced the same warnings/error than I have ?

Regards.