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User1573261788318367's avatar
User1573261788318367
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6 years ago

Stratix 10M DIB timing constraints

Hi all, I have a 20 MHz DUT clock and 400 MHz DIB clock in my design (split across the U1 and U2 dies of the Stratix 10M). In the timing report I"m seeing a lot of violations between these two domai...
KennyT_altera's avatar
KennyT_altera
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6 years ago

What you can do is look into the design example/reference design how they write the PCIE constrain. From there, you should be able to determined which to used in the above.