Forum Discussion

roeekalinsky's avatar
roeekalinsky
Icon for Contributor rankContributor
4 years ago

Stratix 10 UCID IP bug: partition conflict

If the S10 UCID IP is used and its clock input comes from a sector clock gate, Quartus errors out during the fitter stage with the following message: Error (19732): Sector clock gate s10clkctrl_ip_...
roeekalinsky's avatar
roeekalinsky
Icon for Contributor rankContributor
4 years ago

Hi @YuanLi_S_Intel,

Sorry for the ambiguity. "UCID" is an older Altera abbreviation for "Unique Chip ID", and "Stratix 10 UCID IP" in my post refers to the Altera-provided IP module used for reading the unique chip ID in a Stratix 10 device.

The proper name of this IP module is "altera_s10_chip_id", and it is available in Quartus. When a Stratix 10 project is open in the Quartus GUI, see IP Catalog > Library > Basic Functions > Configuration and Programming > Chip ID Intel FPGA IP.

You can also see it instantiated in the trivial design example I provided that demonstrates the issue I reported.

Thanks,
-Roee