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HBhat2's avatar
HBhat2
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7 years ago
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Stratix 10 L tile Native PHY unable to receive incremental data sent from TX and tested using FMC loopback card

Hi, I am using Stratix 10 SoC dev kit and testing the transceiver with FMC loopback card. I tested with the Board test System and all are looking fine with BER = 0. Even I opened the FMCA project ...
Nathan_R_Intel's avatar
Nathan_R_Intel
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7 years ago
Hie Hariprasad, My apologies for the delayed response as I had to take time to get the hardware and test it. I understand your failure. Currently your design cannot close timing, hence suspect this is causing the failure that tx_parallel_data is different from rx_parallel_data. I am trying to address the timing issue when change the tx_coreclkin and rx_coreclkin clocks. I will keep you posted. Regards, Nathan
  • HBhat2's avatar
    HBhat2
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    7 years ago

    Hi @NathanR_Intel​ ,

    Thank you for the update.

    We came to know that Enhanced PCS and PCS direct doesn't support word aligner by default. With this info. I changed the Native PHY config to Enhanced PCS and enabled RX bitslip feature and port.

    Now, I am sending known pattern first and checking the reciever whether it is able to lock for the first time. My observation is it is not locking without bit slip. I am pulsating the bitslip port until rx aligns for the known pattern. Once bitslip is done, then I start transmitting the incremental data.

    Also, one more change I have done in native phy is change the "RX adaptation mode" to adaptive from Manual.

    With this, I am able to receive the data continuously @20.625Gbps without missing any data.

    Please let me know if you have any suggestion on meeting the timing. It will help us with our final implementation using startix10 FPGA.

    With Regards,

    HPB