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HBhat2
Contributor
ContributorStratix 10 L tile Native PHY unable to receive incremental data sent from TX and tested using FMC loopback card
Hi, I am using Stratix 10 SoC dev kit and testing the transceiver with FMC loopback card. I tested with the Board test System and all are looking fine with BER = 0. Even I opened the FMCA project ...
- Hie, Its good news that you can receive the signal correctly. Yes, since you are using PCS direct, there is no word aligner hardware available. Hence, you will need to implement word aligner in the fabric. As for meeting timing in Stratix 10, we have a document to guide you. https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/stratix-10/s10_hp_hb.pdf Please refer to section 2.3 and 2.4 mainly. Please let me know if you need any other information. Regards, Nathan
Nathan_R_IntelContributor
ContributorHie,
Could you please attach your design achieve , .qar instead of just the zip version of the ip files. It will be difficult to analyze the fault with your design without the complete design achieve.
Regards,
Nathan
I have received your design achieve
HBhat2Contributor
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