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HBhat2's avatar
HBhat2
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6 years ago
Solved

Stratix 10 L-Tile FPGA- Native PHY - PCS to PMA interface

Hi, I planned to use PCS Direct between my custom PCS to PMA interface. Custom PCS works with TX_clkout frequency. So, there some cases where I may need to pause data for 1 cycle from Custom PCS to ...
  • Nathan_R_Intel's avatar
    Nathan_R_Intel
    6 years ago

    Hie,

    There is no PMA logic to check the status to read out the data from fifo when using PCS direct. You will need to implement the phase compensation fifo on your customer PCS.

    The no data is present for 1 clock cycle, the serializer will populate itself with all 0s or 1s for the 1 clock cycle. Its equivalent to releasing the PMA out of reset without sending data.

    Regards,

    Nathan

Nathan_R_Intel's avatar
Nathan_R_Intel
Icon for Contributor rankContributor
6 years ago

Hie,

There is no PMA logic to check the status to read out the data from fifo when using PCS direct. You will need to implement the phase compensation fifo on your customer PCS.

The no data is present for 1 clock cycle, the serializer will populate itself with all 0s or 1s for the 1 clock cycle. Its equivalent to releasing the PMA out of reset without sending data.

Regards,

Nathan

HBhat2's avatar
HBhat2
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6 years ago

Hi @NathanR_Intel​ ,

Thank you for your response. I revisited the PMA blocks and agree with "Serializer will populate itself with all 0s or 1s for the 1 clock cycle. Its equivalent to releasing the PMA out of reset without sending data." statement.

With regards,

HPB