Forum Discussion
ContributorStratix 10 L-Tile FPGA- Native PHY - PCS to PMA interface
Hie,
There is no PMA logic to check the status to read out the data from fifo when using PCS direct. You will need to implement the phase compensation fifo on your customer PCS.
The no data is present for 1 clock cycle, the serializer will populate itself with all 0s or 1s for the 1 clock cycle. Its equivalent to releasing the PMA out of reset without sending data.
Regards,
Nathan
ContributorHie,
There is no PMA logic to check the status to read out the data from fifo when using PCS direct. You will need to implement the phase compensation fifo on your customer PCS.
The no data is present for 1 clock cycle, the serializer will populate itself with all 0s or 1s for the 1 clock cycle. Its equivalent to releasing the PMA out of reset without sending data.
Regards,
Nathan
HBhat2Hi @NathanR_Intel ,
Thank you for your response. I revisited the PMA blocks and agree with "Serializer will populate itself with all 0s or 1s for the 1 clock cycle. Its equivalent to releasing the PMA out of reset without sending data." statement.
With regards,
HPB
