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MUrba10's avatar
MUrba10
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5 years ago

Stratix 10 E-TILE reference clock

Hello, I would like to use E-TILE transceiver reference clock input for clocking core logic bypassing transceiver. In "Intel® Stratix® 10 Device Family Pin Connection Guidelines" document in Table ...
Deshi_Intel's avatar
Deshi_Intel
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5 years ago

Hi,

May I know which Quartus version that you used ?

I checked out Etile transcevier PHY user guide doc but didn't find any usage explanation on refclk connection to FPGA core logic.

I believe maybe it's impossible to connect Etile refclk to FPGA core.

  • This could be wrong explanation on Intel® Stratix® 10 Device Family Pin Connection Guidelines table 18.
  • Anyway, pls let me clarify with Intel internal team first then I will get back to you.

Thanks.

Regards,

dlim

MUrba10's avatar
MUrba10
Icon for New Contributor rankNew Contributor
5 years ago

Hello,

Thank you for your answer.

I'm using Quartus 19.3.

I know that Etile transceiver PHY user guide does not contain any information regarding refclk connection to FPGA core logic.

But Intel® Stratix® 10 Device Family Pin Connection Guidelines document does have this information:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/dp/stratix-10/pcg-01020.pdf

Please see page 42, Table 18.

That is why I'm asking.

Thank you!

Best regards,

Mikhail