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Altera_Forum
Honored Contributor
12 years ago --- Quote Start --- A register may be a Z^-1 block. --- Quote End --- yes it is sample delay block(in ModelPrim library) and if set to 1 then infers a register and carries symbol of z^1. BTW xilinx SysGen(equivalent to Altera ADSPBuilder) has delay block as above but also has separate register block. Their register block has ports for reset and enable. Altera's sample block is naked of ports apart from D&Q