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SMS's avatar
SMS
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7 years ago

Soft LVDS IP core bitslip

I am using Max10 and included Soft LVDS IP core for data transmission and reception. For link training I sent 8'h0F. Now, the data at LVDS Rx slips every clock cycle. I have tried to align it u...
SMS's avatar
SMS
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7 years ago

Attached are two projects one for Tx and one for Rx. I am programming the DE10-Lite board (10MDAF484C7G) as Tx and a custom board (10M16SAE144I7G) as Rx.

  • IDeyn's avatar
    IDeyn
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    7 years ago

    Hi SMS,

    I quickly checked your project and I can say that you should begin with a creation of constraint file (sdc).

    You should start with create_clock command, FE create_clock -name {I_ADC_FCO} -period 20.000 -waveform { 0.000 10.000 } [get_ports {I_ADC_FCO}]

    After that and after successful timing analysis you should test if your design works.

    --

    Best regards,

    Ivan