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TSchu3's avatar
TSchu3
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

Simulating Triple Speed Ethernet, Decryption Fails

Hello, I am trying to simulate the TSE testbench IP generated with Quartus Prime Standard 18.0. My simulator is Cadence Xcelium. Xcelium cannot decrypt the TSE testbench submodules. I have not enco...
Deshi_Intel's avatar
Deshi_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

HI Travis,

I carefully read back the EDA support plan table from Quartus release note doc and finally found out the answer is there all the while. Sorry, I didn't catch it earlier.

Let me attached the screen shot and explain to you again.

  • For Cadence sim (IES) for both Quartus std and pro, there is bracket (64-bit Linux only) – I understand now this is referring to support in Linux OS only
  • If we look at Mentor Modelsim SE, it’s bracket (64-bit only) – this means it’s supported on both Win OS and Linux OS
  • If we look at Aldec Active-HDL, it's bracket (32 bits win only) - this means it's supported in Win OS only

I hope I clarify your doubt now.

Thanks.

Regards,

dlim