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TSchu3's avatar
TSchu3
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5 years ago

Simulating Triple Speed Ethernet, Decryption Fails

Hello, I am trying to simulate the TSE testbench IP generated with Quartus Prime Standard 18.0. My simulator is Cadence Xcelium. Xcelium cannot decrypt the TSE testbench submodules. I have not enco...
TSchu3's avatar
TSchu3
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

Thank you for taking the time to look into this. Unfortunately switching FPGAs is not an option nor is switching simulation tools. Both are VERY expensive.

However, There is still one avenue to look into. According to the tables you posted Cadence Incisive should still be supported. Xcelium is backward compatible with Incisive. So if those files were present I could use them. But they are not generated, so something is still not right. Can you try to find out why the Cadence Incisive submodules are not generated?

Thanks again.

Travis