Forum Discussion

Occasional Contributor

3 years ago

Simulating RS232 UART IP Core in VHDL

Hello, I am currently working on a FPGA design containing a UART interface and have choosen the Intel RS232 UART IP Core from the University Program to use for this. I would like to simulate the ...

ShengN_altera

Super Contributor

3 years ago

Hi Florian,

All other device family using VHDL can simulate without error but with this Warning: (vsim-3473). Sorry for missing that warning before. I think still come back to this KDB https://www.intel.com/content/www/us/en/support/programmable/articles/000080465.html where RS232 UART only supported by verilog language for simulation. Verilog language works fine on all device families.

Thanks.

Best Regards

Sheng

FHint

Occasional Contributor

3 years ago

Hi Sheng,

ok, so it doesn't make sense for me to install and test any other additional family when this warning is always going to appear, because without the rs232 instance bound I can't watch its behaviour.

Therefore I'll have to wait until I am able to debug the component in hardware, when it arrives.

I guess the topic can be closed then.

Best Regards,
Florian

Forum Discussion

Simulating RS232 UART IP Core in VHDL

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