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FHint's avatar
FHint
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

Simulating RS232 UART IP Core in VHDL

Hello, I am currently working on a FPGA design containing a UART interface and have choosen the Intel RS232 UART IP Core from the University Program to use for this. I would like to simulate the ...
ShengN_altera's avatar
ShengN_altera
Icon for Super Contributor rankSuper Contributor
3 years ago

Hi Florian,


You can change device family in Quartus main window and create new qsys project. Or go to View/Device Family in platform designer to change it.


May be you can replace RS232 UART with UART {RS-232 Serial Port) Intel FPGA IP as alternative. Both are similar.


Thanks,

Best Regards,

Sheng

p/s: If any answer from community or Intel support are helpful, please feel free to mark as solution and give Kudos.


FHint's avatar
FHint
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

Hi Sheng,

I have installed and tried to use Arria V but it still says that for rs232 no files were generated for fileset SIM_VHDL.
Which device family did you use?

I have tried using the UART you mentioned above, but unfortunately it doesn't support the stream mode that the "old" UART has. It only supports the memory mapped mode.

Best Regards,
Florian