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FHint's avatar
FHint
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

Simulating RS232 UART IP Core in VHDL

Hello, I am currently working on a FPGA design containing a UART interface and have choosen the Intel RS232 UART IP Core from the University Program to use for this. I would like to simulate the ...
ShengN_altera's avatar
ShengN_altera
Icon for Super Contributor rankSuper Contributor
3 years ago

Hi Florian,


Any further update or consideration? Or should I consider that case to be closed?


Best regards,

Sheng

p/s: If any answer from community or Intel support are helpful, please feel free to mark as solution and give Kudos.


  • FHint's avatar
    FHint
    Icon for Occasional Contributor rankOccasional Contributor
    3 years ago

    Hi Sheng,

    when opening the unsaved_tb.qsys the same error as mentioned above appears again. The component "unsaved 1.0" wasn't found or could not be instantiated.

    I am not really sure what I should expect if the unsaved_tb.qsys worked - my problem will still be that I can not run my VHDL simulation without the VHDL model of the RS232 IP core. This won't change with the files you sent me, does it?

    As long as there is no way to include the RS232 IP core in a qsys testbench generated as VHDL I cannot continue with it.

    Best Regards,
    Florian