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FHint's avatar
FHint
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

Simulating RS232 UART IP Core in VHDL

Hello, I am currently working on a FPGA design containing a UART interface and have choosen the Intel RS232 UART IP Core from the University Program to use for this. I would like to simulate the ...
FHint's avatar
FHint
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

Hi Sheng,

I have tried to take a look at the unsaved_tb.qsys system you had attached, but the platform designer cannot find the component, as you can see in the following image.

I am using the Quartus Standard 19.1 edition - is that a problem?

Best Regards,
Florian

ShengN_altera's avatar
ShengN_altera
Icon for Super Contributor rankSuper Contributor
3 years ago

Hi Florian,

I think there are some files missing there. Below attach another file for your reference. Try to remove unsaved.qsys and include only unsaved_tb.qsys which is .qsys file of testbench system generated. Then do compilation and RTL simulation. You can add more signals by right-clicking in modelsim object panel or use command add wave -r /*

Best regards,
Sheng
p/s: If any answer from community or Intel support are helpful, please feel free to mark as solution and give Kudos.