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FHint's avatar
FHint
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

Simulating RS232 UART IP Core in VHDL

Hello, I am currently working on a FPGA design containing a UART interface and have choosen the Intel RS232 UART IP Core from the University Program to use for this. I would like to simulate the ...
ShengN_altera's avatar
ShengN_altera
Icon for Super Contributor rankSuper Contributor
3 years ago

Hi Florian,

Sorry for confusion. I think you might be using other device family. You may have to include the .qsys file to include all the submodules.

(If still cannot you have to use Modelsim Simulation Setup Script msim_setup.tcl in sim/Mentor. Refer to manual here or video here.)