Forum Discussion

FHint's avatar
FHint
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

Simulating RS232 UART IP Core in VHDL

Hello, I am currently working on a FPGA design containing a UART interface and have choosen the Intel RS232 UART IP Core from the University Program to use for this. I would like to simulate the ...
ShengN_altera's avatar
ShengN_altera
Icon for Super Contributor rankSuper Contributor
3 years ago

Hi Florian,

You are using standard version right? This <subsystem_name>\altera_up_avalon_rs232_171\synth file format you mention can only be created by pro version but not standard version. If for standard version usually there will be synthesis, simulation or testbench files generated based on your choice. Below attached an uart RS232 ip core project file created using Quartus 19.1 Standard for your reference.

Thanks,

Best Regards,

Sheng