Forum Discussion
Altera_Forum
Honored Contributor
12 years agoYou should be able to already simulate your design, since it should have produced a .vo file for the VHDL that is included by the .do scripts.
It gets awkward when you need to actively edit the VHDL and rerun your simulation. The best I came up with was to modify the VHDL in a separate Quartus project that compiled it to .vo, which then got included in the primary Modelsim environment. It was not a very productive arrangement, but I didn't need to work in it too much so it was OK.