simulate an LVDS soft core IP

Hi,

I have the same error using Quartus Prime 18.1.0 Build 625 9/12/2018 SJ Lite version

and

ModelSim - INTEL FPGA STARTER EDITION 10.5b Revision: 2016.10 Date: Oct 5 2016.

Device: Cyclone10 as on Arduino VIDOR4000 board to be used for students.

Circuit: a simple 7-bit counter.

Log transcript on Modelsim:

# vsim -gui -l msim_transcript -L cyclone10lp_ver -L work testbench

# Start time: 12:07:41 on Jan 06,2019

# Loading work.testbench

# Loading work.prove_project

# Loading cyclone10lp_ver.cyclone10lp_io_obuf

# Loading cyclone10lp_ver.cyclone10lp_io_ibuf

# Loading cyclone10lp_ver.cyclone10lp_lcell_comb

# ** Error: (vsim-3033) prove_project.vo(1998): Instantiation of 'dffeas' failed. The design unit was not found.

# Time: 0 ps Iteration: 0 Instance: /testbench/pproj File: prove_project.vo

# Searched libraries:

# C:/intelFPGA/18.1/modelsim_ase/altera/verilog/cyclone10lp

# D:/PROGETTI/ARDUINO/Vidor4000/projects/prova/simulation/modelsim/gate_work

Thanks for the help.

Fabio