SGDMA streaming to memory, how to start and stop?

It seems to me that all you need to do is modify your IP to have an enable bit so that you can make sure the DMA is ready before you enable the core that is streaming the data. While your core is disabled it's valid bit should be driven low (that's the point of the valid signal, to control the transfer of streaming data). Then you just need to make sure you keep the DMA engine filled with descriptors so that it can keep up with the rate of data entering it (which is probably much easier to achieve using the mSGDMA).

If you switch to the mSGDMA there is a bit inside the dispatcher called "busy" which you could pull out but I think trying to coordinate to IP cores like this will be rather painful. I would just use the flow control built into the ST spec and just coordinate starting both IPs instead.