Forum Discussion
Occasional ContributorSerial Lite Interface IP - FAQ
Hi,
As I understand it, you have some inquiries related to the SerialLite IP for FPGA. For your information, you may explore into the Serial Lite III IP and refer to the following user guide for further details:
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_slite3_streaming.pdf
Regarding your inquiry on the maximum lanes can be supported, as I understand it, this would be dependent on the device that you are using. You may refer to the "Performance and Resource Utilization" section in the uesr guide for further details.
Please let me know if there is any concern. Thank you.
Best regards,
Chee Pin
Regular ContributorHi,
As I understand it, you have some inquiries related to the SerialLite IP for FPGA. For your information, you may explore into the Serial Lite III IP and refer to the following user guide for further details:
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_slite3_streaming.pdf
Regarding your inquiry on the maximum lanes can be supported, as I understand it, this would be dependent on the device that you are using. You may refer to the "Performance and Resource Utilization" section in the uesr guide for further details.
Please let me know if there is any concern. Thank you.
Best regards,
Chee Pin
