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JStan7's avatar
JStan7
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6 years ago

SDRAM controller Open Row Management

I use the Intel SDRAM controller described in 'ug_embedded_ip.pdf' [section 32] and found in 32.2.4.1 Open Row Management: ... SDRAM chips are arranged as multiple banks of memory, in which each ban...
JStan7's avatar
JStan7
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6 years ago

I want to use an old SDRAM (single data rate, no DDRx) in combination with Cyclone 10LP because of price sensitive product. But Cyclone 10 LP doesn't support DDR (unfortunately)

so I think for the combination e.g. 10CL016 + MT48LC16M16 there is no support for interleaving bank access

NurAida_A_Intel's avatar
NurAida_A_Intel
Icon for Frequent Contributor rankFrequent Contributor
6 years ago

Dear JStan7,

If you are interested to use DDR support, then I recommend you to use Cyclone 10 GX family which support DDR3 also offering a performance advantage for cost-sensitive applications. For more details, please refer to this product table: https://www.intel.com/content/www/us/en/products/programmable/fpga/cyclone-10.html

If you want to use DDR3 with cheapest, the best option is using Cyclone V. In case, you want to consider using DDR2 IP, then my suggestion for you is go for Max 10 with I7 or C7 speed grade.

For more details on the device and EMIF support, you may refer to this EMIF spec : https://www.intel.com/content/www/us/en/programmable/support/support-resources/support-centers/external-memory-interfaces-support/emif.html

Thanks

Regards,

NAli1