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JStan7's avatar
JStan7
Icon for New Contributor rankNew Contributor
7 years ago

SDRAM controller Open Row Management

I use the Intel SDRAM controller described in 'ug_embedded_ip.pdf' [section 32] and found in 32.2.4.1 Open Row Management: ... SDRAM chips are arranged as multiple banks of memory, in which each ban...
sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
7 years ago

I presume you're talking about this document:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_embedded_ip.pdf

This is referencing the old SDRAM IP that only supports the old PC100 standard, not DDR. So it does not support the features you mention. If you are in fact using DDR memory, you should take a look at the modern EMIF IP which does support these features:

https://www.intel.com/content/www/us/en/programmable/support/literature/lit-external-memory-interface.html

https://www.intel.com/content/www/us/en/programmable/support/support-resources/support-centers/external-memory-interfaces-support.html

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