Forum Discussion
AlexR
New Contributor
7 years agoSDI II IP - TX sync Issue
Hi, In the CycloneV GX project, I configured the SDI II core as follows: bidir, 3G SDI only, transceiver and protocol, CMU, dynamic switching off. I found out that the SDI output in my project is...
SengKok_L_Intel
Regular Contributor
7 years agoYes, you are right. Each Transceiver bank in Stratix V device has 6 channels (2 CMU PLL), but for cyclone V, each transceiver bank has 3 channels (1 CMU PLL).
Regards -SK