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AlexR
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7 years ago

SDI II IP - TX sync Issue

Hi, In the CycloneV GX project, I configured the SDI II core as follows: bidir, 3G SDI only, transceiver and protocol, CMU, dynamic switching off. I found out that the SDI output in my project is...
AlexR's avatar
AlexR
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7 years ago

Hi SK Lim,

>Each Transceiver bank has 6 channels with two CMU PLLs that you can use for the duplex SDI loopback.

I wanted to clarify: there are two CMUs in each bank or in the whole chip? Chip is 5CGXFC4C6F23. I placed in the project two channels SDI loopback. Below is a screenshot from the Chip Planner ("канал"="channel"). The third channel does not fit, as there is not enough space for the location of the third channel cmu_pll.tx_pll.

Thanks for your help.

Best regards, Aleksander