Forum Discussion

AlexR's avatar
AlexR
Icon for New Contributor rankNew Contributor
7 years ago

SDI II IP - TX sync Issue

Hi, In the CycloneV GX project, I configured the SDI II core as follows: bidir, 3G SDI only, transceiver and protocol, CMU, dynamic switching off. I found out that the SDI output in my project is...
SengKok_L_Intel's avatar
SengKok_L_Intel
Icon for Regular Contributor rankRegular Contributor
7 years ago

Hi,

  1. Just to clarify. Do you mean that if you connect the tx_coreclk to ExtClear_pclk, then the problem appears? As per the user guide, the tx_coreclk must be always stable and it can share with xcvr_refclk. If the ExtClear_plck is a clean & stable clock, why not it used as refclk for SDI TX if this is coming from the transceiver dedicated clock pin? Are you implement SDI loopback as SDI RX -> FIFO -> SDI TX? If yes, probably the example in alterawiki is helpful to you. https://fpgawiki.intel.com/wiki/Triple-rate_SDI_II_Reference_Design_for_Stratix_V,_Arria_V_%26_Cyclone_V_devices
  2. You do not need to perform TX clock switching but the SDI II IP is still required to connect to the reconfiguration controller.

Regards -SK