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ZWang142's avatar
ZWang142
Icon for New Contributor rankNew Contributor
5 years ago

s10 pcie avmm core does not send out memory read data

I'm simulating the s10 pcie avmm core in the bridge mode, gen3 x4, 256-bit avmm data bus. From the RP model, I sent a 64-byte write request and then a 64-byte read request at the same address. From ...
SengKok_L_Intel's avatar
SengKok_L_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi Sir,

I have just tested it by using Quartus v20.1, I've generated the PCIe gen3x4 example design, and then run the simulation in ModelSim SE, everything works fine, and I can see the rx_st* as well as tx_st* signals are toggling. I would suggest you to use the examples design to run the simulation if you haven't done so.

Regards -SK