New ContributorHii i am working on SATA protocol on stratix IV FPGA.I am using altgx ip for the same. so the signal rx_signaldetect is always low in hardware when I checked with signal tap logic analyzer and i have checked the threshhold level with both 2 and 6 but rx_signaldetect always remains low.
can anyone please help me solve this.
Regular ContributorThe rx_signaldetect is a signal used to indicate whether the signal level present at the receiver input buffer. If this signal is low, you probably need to debug it from the hardware connection perspective, to determine whether there is any connection issue or signal integrity issue.
If possible, you may perform the serial loopback test, and see if the CDR can be locked, this is to ensure there is no concern about your FPGA design implementation.
Regards -SK
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