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MPerg
New Contributor
New ContributorReport DDR timing report - negative slack meaning
Hello, I'm using Arria10 FPGA with 2 DDR controllers: One is connected to HPS and the other is connected to FPGA logic. When I run TimeQuest analysis I get under report DDR report negative slack o...
BoonT_Intel
Frequent Contributor
Frequent ContributorHi Sir,
The negative value on the "memory calibration" is expected and ok as long as the final (sum up) value is positive (last row) - for your first screenshot, it is "Final write leveling margin".
In conclusion, the timing is ok as long as you do not receive critical warning said "DDR timing not met" in quartus timing report.
Hope this helps😃
