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RBerm3's avatar
RBerm3
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6 years ago

Remote Update IP not reporting CRC error

FPGA: Cyclone 10 GX 10CX150YF672I6G Tools: Quartus Prime Pro 17.1.2 build 304 Flash: Micron MT25QU512ABB (EPCQL512) I have programed the FPGA with 2 images - factory and application. The factory...
ShafiqY_Intel's avatar
ShafiqY_Intel
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6 years ago

Hi RBern3,

I suspect you are enabled the "Enable reconfig POF checking" in Remote Update IP parameters.

Please disable this parameters to make CRC error detection working.

Kindly try it out with your design and let us know the result.

ThanksšŸ˜‰ šŸ˜‰ šŸ˜‰

  • RBerm3's avatar
    RBerm3
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    6 years ago

    Hi Mshafiq,

    Actually the parameter ā€œEnable reconfig POF checkingā€ is disabled (grayed out) in the IP parameters menu.

    The RU IP user guide states about this parameter:

    ā€œNot available as this option is handled by the FPGA AS

    controller instead of the Remote Update Intel FPGA IP

    core. The same application image is loaded for three

    times before reverting to factory application image, to

    ensure no unexpected system failure occurred.ā€

    Also I tried to disable and enable the ā€œAuto-restart configuration after errorā€ option ā€œfrom the device and pin optionsā€œ menu.

    No luck so far.

    Please advise ,

    Thanks Roman.

    • ShafiqY_Intel's avatar
      ShafiqY_Intel
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      6 years ago

      Hi Roman,

      I'm sorry I missed that you are using Cyclone 10 GX (this device didn't have POF checking option).

      If I'm not mistaken, POF checking option already embedded for Cyclone 10 GX (you can't disable it anymore.)

      Another thing that I suspect is Remote Update IP detect your programming file as Blank. Since you are erasing the first sector (offset 0x01000000) of the application image, Remote Update IP detect as Blank file, not corrupted file. Therefore, the ā€œReconfiguration trigger Conditionsā€ parameter state show 0x0 (bit 0 - no CRC error), because the file is blank not corrupted.

      Maybe you can try to corrupt the first sector (offset 0x01000000) by replace it with Random bit rather than erase it. Let me know if this is working.

      I wondering when you mention ā€œReconfiguration trigger Conditionsā€ parameter state 0x0 (no error), do you mean only bit 0 is 0x0(no error)? Or for all bit 0-4 is 0x0?

      Some of bit 0-4 should trigger when you able to load to Factory Image.

      Thanks.šŸ˜‰ šŸ˜‰ šŸ˜‰

    • RBerm3's avatar
      RBerm3
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      6 years ago

      ā€‹ Hi Mshafiq,

      I tried to corrupt the first sector,

      When I corrupt the first page (offset 0x01000000) after POR the application image loads correctly from the flash and the all bits of ā€œreconfiguration triggerā€ is ā€˜0ā€™.

      When I corrupt the second page of the first sector (offset 0x01000100) the factory image loads and the ā€œreconfiguration triggerā€ bit 0 is ā€˜1ā€™ (0x1).

      When I erase the whole sector the factory image loads and all the bits of ā€œreconfiguration triggerā€ is ā€˜0ā€™.

      Thank for your help,

      Roman.

    • ShafiqY_Intel's avatar
      ShafiqY_Intel
      Icon for Frequent Contributor rankFrequent Contributor
      6 years ago

      Hi,

      I'm really apologize for late reply. I got an urgent project in last month.

      May I know your status in this issue? Are you able to solve and find the solution?

      šŸ˜‰