Contributor
Regular ContributorHi,
Thank you for your question regarding implementing a simple test design with the Agilex 5 GTS transceiver.
To help you get started quickly, I recommend referring to the IP-generated example design described in the GTS Transceiver PHY User Guide under the section “GTS PMA/FEC Direct PHY IP Example Design.” You can select an example design that is closest to your target configuration, verify its functionality, and then proceed with customizing it to meet your specific requirements. Generally the example designs support simulation and hardware.
Please let me know if you have any further questions or need additional clarification. Thank you.
ContributorHi CheepinC_altera,
Thanks for your note! I have indeed looked into this already.
As far as I can tell, I think it must be an issue with the reset sequence, as the data does seem to loopback correctly every so often. This may indicate an issue with the CDR lock, right? Especially as signal taps reports that the on the TX parallel bus is as expected each time.
I am hoping someone might notice what I have done differently enough from the reference designs to cause this intermittent issue.
I have combed through both my design above and the reference design a few times and seem to keep missing whatever the key difference is.
Many thanks
Regular ContributorHi,
One possible cause of intermittent bit errors could be related to signal integrity issues. Have you had a chance to enable serial loopback and check if the issue persists? This step can help isolate whether the problem is due to signal integrity or something else.
