Quartus MSGDMA core Empty bits when used from Avalon ST to Memory Mapped transfer

Hi,

Empty bits signal is only available when Packet Support Enable is used. If check this note:

31.3.1.4. Parameters (intel.com)

Note: When PACKET_ENABLE parameter is disabled and TRANSFER_TYPE is not "Full Word Accesses Only", any unaligned transfer length will cause additional bytes to be written during the last transfer beat of the Avalon® streaming data source port of the read host core. Only with this parameter set TRUE, actual bytes transferred is meaningful for the transaction. So I would say that DMA will just write the relevant bytes to memory

Quartus MSGDMA core Empty bits when used from Avalon ST to Memory Mapped transfer On an Avalon-ST to Memory mapped DMA transfer, if Empty bits are set, on the Avalon ST bus, what happens to a 32 bit Memory mapped transfer, does the DMA just write the relevant bytes to memory?

Based on RTL and simulation, empty bits will be written to FIFO when EOP is high.