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NGord's avatar
NGord
Icon for Occasional Contributor rankOccasional Contributor
2 years ago
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Quartus MSGDMA core Empty bits when used from Avalon ST to Memory Mapped transfer

On an Avalon-ST to Memory mapped DMA transfer, if Empty bits are set, on the Avalon ST bus, what happens to a 32 bit Memory mapped transfer, does the DMA just write the relevant bytes to memory?
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  • ShengN_altera's avatar
    ShengN_altera
    2 years ago

    Hi,

    If using the Packet Support Enable feature, Empty bits signal will be available. With this feature enabled, actual bytes (no additional bytes) will be transferred for the transaction. So I would say that DMA will just write the relevant bytes to memory as mentioned before.

    Thanks,

    Sheng

NGord's avatar
NGord
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

Set DMA mode to Streaming to Memory mapped
Set to '32 bit data width'
Set 'Packet Support Enable'
This will create two Empty bit signals for the Avalon-ST bus which show which of the 4 bytes on the ST side carry valid data.
I want to know what the Memory mapped side does when it sees any of these Empty bits set.
Will it use the Byte enable signals to write only the relevant bytes or does it ignore Empty bit setting?