quartus 19.4 can not use more than 2 clocked video output II IP at one project?

Hi,

1. May I know is this Quartus synthesis error or fitter error ?
2. Also have you traced the design files as indicated in the error message, is the error coming from CVO IP used to interact with HDMI IP or SDI IP ?

I checked VIP user guide on the usage of sdi_cvo_rden.

• https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_vip.pdf
• Have you enabled this port correctly as shown in (page 79, table 31) and also connect the port correctly as shown in (page 29, figure 14) ?

Thanks.

Regards,

dlim