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WKett's avatar
WKett
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6 years ago

Quartus 18.1 Soft LVDS transmitter w/ ext PLL core missing tx_outclock ddio generator logic?

If I generate a Soft LVDS Intel FPGA IP core (v18.1) transmitter (verilog) and do not select the external PLL option, 7x serialization factor (odd), and 4 output channels, the generated verilog shows...
WKett's avatar
WKett
Icon for New Contributor rankNew Contributor
6 years ago

Yes, that concerns me too. I assume you have access to my profile and can send a private email. Can you please tell me the criteria for getting an approved premium support account. Paid premium software? Hi budget sales account? What? My request was denied last week with no explanation and I can't find the criteria posted anywhere. I have worked with Altera FPGAs since before the Cyclone I device was released and have submitted numerous bugs through our FAE over the years. Now that I changed jobs and Intel acquired Altera, I can't even submit a decent bug report. Does Intel want folks to switch over to other brands or something?