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WKett
New Contributor
New ContributorQuartus 18.1 Soft LVDS transmitter w/ ext PLL core missing tx_outclock ddio generator logic?
If I generate a Soft LVDS Intel FPGA IP core (v18.1) transmitter (verilog) and do not select the external PLL option, 7x serialization factor (odd), and 4 output channels, the generated verilog shows...
WKettNew Contributor
New ContributorMax10 family. Quartus 18.1 like it says in my post subject line. Specifically targeting 10M04DCU324C8G with 10M08DC or 10M16DC as the migration path.
