Quartus 16: Can't find port "reset" in OpenCore Plus entity "alt_vip_cvo_core"

Hi,

I have some problems on display port IP core. The Displa Port AUX interface have "aux_in,aux_oe,aux_out" signal. But on my Altera Arria10 SoC Development Kits, there have "DP_AUX_DE DP_AUX_D DP_AUX_REn DP_AUX_R" signal,how can I constraint the Display Port IP Core AUX signal to the FPGA Board?

Thanks//BR