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jrrguzman's avatar
jrrguzman
Icon for Occasional Contributor rankOccasional Contributor
6 years ago
Solved

Qsys execution within modelsim

Hi, I'm trying to automate my simulation environment in Modelsim which uses an Intel Avalon MM master BFM. I want to generate all the required scripts within Modelsim, so I only need to pass the qs...
  • jrrguzman's avatar
    jrrguzman
    6 years ago

    Hi @Vicky​ ,

    Unfortunately your links didn't work...it seems Modelsim does not like how qsys-generate ends up, so I can't call it from within Modelsim.

    However, I found a workaround that works quite ok. So instead of calling qsys-generate within Modelsim, I execute a tcl script in quartus that first executes the qsys-generate and when all the sources are generated, launches Modelsim with an attached do file, for setting up the simulation environment and compilation dependencies.

    Cheers

AndyN's avatar
AndyN
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

What's the specific error that Modelsim is throwing?

  • jrrguzman's avatar
    jrrguzman
    Icon for Occasional Contributor rankOccasional Contributor
    6 years ago

    Hi @AndyN​,

    Basically it spits out the output of the qsys-generate execution:

    # Error in macro ./testbench.do line 67

    # 2019.08.09.08:14:16 Info: Saving generation log to C:/Projects/fw_cores/common_files/tags/Iss1Rev3/sim/avl_mm_bfm/avl_mm_bfm/avl_mm_bfm_generation.rpt

    # 2019.08.09.08:14:16 Info: Starting: <b>Create simulation model</b>

    # 2019.08.09.08:14:16 Info: qsys-generate C:\Projects\fw_cores\common_files\tags\Iss1Rev3\sim\avl_mm_bfm\avl_mm_bfm.qsys --simulation=VHDL --allow-mixed-language-simulation --output-directory=C:\Projects\fw_cores\common_files\tags\Iss1Rev3\sim\avl_mm_bfm\avl_mm_bfm --family="Arria 10" --part=10AS066N3F40E2SG

    # 2019.08.09.08:14:16 Info: Loading avl_mm_bfm/avl_mm_bfm.qsys

    # 2019.08.09.08:14:16 Info: Reading input file

    # 2019.08.09.08:14:16 Info: Adding mm_master_bfm_0 [altera_avalon_mm_master_bfm 17.0]

    # 2019.08.09.08:14:16 Info: Parameterizing module mm_master_bfm_0

    # 2019.08.09.08:14:16 Info: Building connections

    # 2019.08.09.08:14:16 Info: Parameterizing connections

    # 2019.08.09.08:14:16 Info: Validating

    # 2019.08.09.08:14:16 Info: Done reading input file

    # 2019.08.09.08:14:16 Info: avl_mm_bfm: "Transforming system: avl_mm_bfm"

    # 2019.08.09.08:14:16 Info: avl_mm_bfm: Running transform <b>generation_view_transform</b>

    # 2019.08.09.08:14:16 Info: avl_mm_bfm: Running transform <b>generation_view_transform</b> took 0.000s

    # 2019.08.09.08:14:16 Info: mm_master_bfm_0: Running transform <b>generation_view_transform</b>

    # 2019.08.09.08:14:16 Info: mm_master_bfm_0: Running transform <b>generation_view_transform</b> took 0.000s

    # 2019.08.09.08:14:17 Info: avl_mm_bfm: Running transform <b>merlin_avalon_transform</b>

    # 2019.08.09.08:14:17 Info: avl_mm_bfm: Running transform <b>merlin_avalon_transform</b> took 0.032s

    # 2019.08.09.08:14:17 Info: avl_mm_bfm: "Naming system components in system: avl_mm_bfm"

    # 2019.08.09.08:14:17 Info: avl_mm_bfm: "Processing generation queue"

    # 2019.08.09.08:14:17 Info: avl_mm_bfm: "Generating: avl_mm_bfm"

    # 2019.08.09.08:14:17 Info: avl_mm_bfm: "Generating: altera_avalon_mm_master_bfm_vhdl"

    # 2019.08.09.08:14:17 Info: avl_mm_bfm: Done "<b>avl_mm_bfm</b>" with 2 modules, 13 files

    # 2019.08.09.08:14:17 Info: qsys-generate succeeded.

    # 2019.08.09.08:14:17 Info: Finished: <b>Create simulation model</b>

    # 2019.08.09.08:14:17 Info: Starting: <b>Create Modelsim Project.</b>

    # 2019.08.09.08:14:17 Info: sim-script-gen --spd=C:\Projects\fw_cores\common_files\tags\Iss1Rev3\sim\avl_mm_bfm\avl_mm_bfm\avl_mm_bfm.spd --output-directory=C:/Projects/fw_cores/common_files/tags/Iss1Rev3/sim/avl_mm_bfm/avl_mm_bfm/sim/ --use-relative-paths=true

    # 2019.08.09.08:14:17 Info: Doing: <b>ip-make-simscript --spd=C:\Projects\fw_cores\common_files\tags\Iss1Rev3\sim\avl_mm_bfm\avl_mm_bfm\avl_mm_bfm.spd --output-directory=C:/Projects/fw_cores/common_files/tags/Iss1Rev3/sim/avl_mm_bfm/avl_mm_bfm/sim/ --use-relative-paths=true</b>

    # 2019.08.09.08:14:23 Info: Generating the following file(s) for <b>MODELSIM</b> simulator in <b>C:/Projects/fw_cores/common_files/tags/Iss1Rev3/sim/avl_mm_bfm/avl_mm_bfm/sim/</b> directory:

    # 2019.08.09.08:14:23 Info: <b>mentor/msim_setup.tcl</b>

    # 2019.08.09.08:14:23 Info: Skipping <b>VCS</b> script generation since VHDL file $QUARTUS_INSTALL_DIR/eda/sim_lib/altera_syn_attributes.vhd is required for simulation

    # 2019.08.09.08:14:23 Info: Generating the following file(s) for <b>VCSMX</b> simulator in <b>C:/Projects/fw_cores/common_files/tags/Iss1Rev3/sim/avl_mm_bfm/avl_mm_bfm/sim/</b> directory:

    # 2019.08.09.08:14:23 Info: <b>synopsys/vcsmx/synopsys_sim.setup</b>

    # 2019.08.09.08:14:23 Info: <b>synopsys/vcsmx/vcsmx_setup.sh</b>

    # 2019.08.09.08:14:23 Info: Generating the following file(s) for <b>NCSIM</b> simulator in <b>C:/Projects/fw_cores/common_files/tags/Iss1Rev3/sim/avl_mm_bfm/avl_mm_bfm/sim/</b> directory:

    # 2019.08.09.08:14:23 Info: <b>cadence/cds.lib</b>

    # 2019.08.09.08:14:23 Info: <b>cadence/hdl.var</b>

    # 2019.08.09.08:14:23 Info: <b>cadence/ncsim_setup.sh</b>

    # 2019.08.09.08:14:23 Info: <b>2 .cds.lib files</b> in <b>cadence/cds_libs/</b> directory

    # 2019.08.09.08:14:23 Info: Generating the following file(s) for <b>RIVIERA</b> simulator in <b>C:/Projects/fw_cores/common_files/tags/Iss1Rev3/sim/avl_mm_bfm/avl_mm_bfm/sim/</b> directory:

    # 2019.08.09.08:14:23 Info: <b>aldec/rivierapro_setup.tcl</b>

    # 2019.08.09.08:14:23 Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under C:/Projects/fw_cores/common_files/tags/Iss1Rev3/sim/avl_mm_bfm/avl_mm_bfm/sim/.

    # 2019.08.09.08:14:23 Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project.

    # 2019.08.09.08:14:23 Info: Finished: <b>Create Modelsim Project.</b>

    # 2019.08.09.08:14:23 Info:

    # 2019.08.09.08:14:23 Info: Starting: <b>Create HDL design files for synthesis</b>

    # 2019.08.09.08:14:23 Info: qsys-generate C:\Projects\fw_cores\common_files\tags\Iss1Rev3\sim\avl_mm_bfm\avl_mm_bfm.qsys --synthesis=VHDL --output-directory=C:\Projects\fw_cores\common_files\tags\Iss1Rev3\sim\avl_mm_bfm\avl_mm_bfm --family="Arria 10" --part=10AS066N3F40E2SG

    # 2019.08.09.08:14:23 Info: Loading avl_mm_bfm/avl_mm_bfm.qsys

    # 2019.08.09.08:14:23 Info: Reading input file

    # 2019.08.09.08:14:23 Info: Adding mm_master_bfm_0 [altera_avalon_mm_master_bfm 17.0]

    # 2019.08.09.08:14:23 Info: Parameterizing module mm_master_bfm_0

    # 2019.08.09.08:14:23 Info: Building connections

    # 2019.08.09.08:14:23 Info: Parameterizing connections

    # 2019.08.09.08:14:23 Info: Validating

    # 2019.08.09.08:14:23 Info: Done reading input file

    # 2019.08.09.08:14:23 Info: avl_mm_bfm: "Transforming system: avl_mm_bfm"

    # 2019.08.09.08:14:23 Info: avl_mm_bfm: Running transform <b>generation_view_transform</b>

    # 2019.08.09.08:14:23 Info: avl_mm_bfm: Running transform <b>generation_view_transform</b> took 0.000s

    # 2019.08.09.08:14:23 Info: mm_master_bfm_0: Running transform <b>generation_view_transform</b>

    # 2019.08.09.08:14:23 Info: mm_master_bfm_0: Running transform <b>generation_view_transform</b> took 0.000s

    # 2019.08.09.08:14:23 Info: avl_mm_bfm: Running transform <b>merlin_avalon_transform</b>

    # 2019.08.09.08:14:23 Info: avl_mm_bfm: Running transform <b>merlin_avalon_transform</b> took 0.023s

    # 2019.08.09.08:14:23 Info: avl_mm_bfm: "Naming system components in system: avl_mm_bfm"

    # 2019.08.09.08:14:23 Info: avl_mm_bfm: "Processing generation queue"

    # 2019.08.09.08:14:23 Info: avl_mm_bfm: "Generating: avl_mm_bfm"

    # 2019.08.09.08:14:23 Info: avl_mm_bfm: "Generating: altera_avalon_mm_master_bfm"

    # 2019.08.09.08:14:23 Info: avl_mm_bfm: Done "<b>avl_mm_bfm</b>" with 2 modules, 6 files

    # 2019.08.09.08:14:23 Info: qsys-generate succeeded.

    # 2019.08.09.08:14:23 Info: Finished: <b>Create HDL design files for synthesis</b>

    # Picked up _JAVA_OPTIONS: -Xmx512M

    # while executing

    # "exec $sopc_path/qsys-generate $filename --synthesis=VHDL --simulation=VHDL --output-directory=$dir/$folder --family="Arria 10" --part=10AS066N3F40E2SG..."