Forum Discussion
JMiret
New Contributor
4 years agoQ20.2: Critical Warning (19166): For IOPLL feedback delay chain setting was reduced from "X" to "0"
Quartus Prime Version 20.2.0 Build 50 06/11/2020 SC Pro Edition Copyright (C) 2020 Intel Corporation. All rights reserved.
Target FPGAs:
"1SX280HU2F50E1VGAS" "1SX280HU1F50E2VG"
"1SX280...
Ash_R_Altera
Regular Contributor
4 years agoOne way is to reduce the fanout of the PLL output clock.
This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you