New ContributorPlanned to Migrate Ptile PCIe to Htile PCIe, but the below Ptile PCIe signals not availble in Htile PCIe IP. Application layer uses the p0_rx_st_hdr_o signal, so need to know how to handle this in Htile IP.
>>>>>>>>>>>>>>>>>
p0_rx_st_hdr_o
p0_rx_st_tlp_prfx_o
p0_rx_st_bar_range_o
p0_rx_st_tlp_abort_o
p0_rx_par_err_o
>>>>>>>>>>>>>>>>>
Thanks!
Frequent ContributorHi ,
Kindly allow me some time to look on your issue
Frequent ContributorHi ,
I understand your concern, to clarify your question.
The Ptile supports different type of configuration (1x16, 2x8 or 4x4) , so the value of below signal will change depends up on the configration.
p0_rx_st_data_o[127:0], p0_rx_st_hdr_o[127:0] and
p0_rx_st_tlp_prfx_o[31:0].
Ref:
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_ptile_pcie_avst.pdf
page no:41
But the same is not been in the S10 H tile device
Ref:
Page no:52
New ContributorHi,
we need x8 configuration, so in Ptile the P1 interface driven by "0" and only P0 interface is used for application layer transaction.
>>>> H tile bus width details >>>>
p0_rx_st_data_o[256:0], p0_rx_st_hdr_o[127:0] and
p0_rx_st_tlp_prfx_o[31:0].
>>>>>>>>>>>>>>>>>>>>>>>>>>>
While migrate to Htile we are choosing Gen3x8,256bit configuration. Am also referring the documents which you shared in this thread. In Htile, seems like header information is available in the data bus itself.
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/archives/ug-s10-pcie-avst-17.1ir1.pdf [page no : 53.]
If my understanding is correct, I need to add glue logic to handle this variation or any adapter is availble to separate the header information from the data bus.
If my understanding is not correct, please provide the correct direction.
