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Altera_Forum
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14 years ago

problem with PCIe troughput in CIV GX DevKit

hi friends i have a problem with the PCIe in the cyclone IV FPGA: i have implement the PCIe HIP using Qsys on Quartus II 11.0 with the modular SGDMA and a On-Chip-Memory. i connect the CIV...
Altera_Forum's avatar
Altera_Forum
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11 years ago

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Dit it happen on the same PC - one time the core negotiated to x1 and another time to x4?

I have an issue, that PCIe core in a custom board on one PC always negotiates to x4 and on the other - always to x1.

What could be the cause?

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The PCIe board was plugged into a OneStopSystems external motherboard, which was in turn connected to a PCIe bridge over to a laptop. I didn't try a "regular" PC motherboard. The fact that I could not simulate with PCIe BFMs made me give up on using Altera's PCIe solutions. If that situation has changed, then I'll look at them again.

I'm not sure what causes the lane width error. If I cared enough (which I did not at the time), I would have used SignalTap II to look at the link training state machine and see if it produced errors. Basically you need to read the PCIe specification and find out where in the link training the width is determined, and then trace that sequence to see what is going wrong.

Cheers,

Dave