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Altera_Forum
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11 years ago

PLL driving ALTCLKCTRL routing CYCLONE IV E

Hi Folks, -Cyclone IV E I have a PLL whose output I feed to an ALTCLKCTRL IP with an enable, the output of which feeds a CLK output pin on the device. When compiling I get the followi...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

I think I may have stumbled upon something...

I have selected the CLKCTRL such that it is not driving the Global clock network but an external clock output. But this generates a different warning...

Warning (10651): VHDL Assertion Statement at PULSEPICKER.vhd(92): assertion is false - report "MGL_INTERNAL_WARNING: ( The parameter value is not one of the pre-specified values in the value list.) altclkctrl|stratixii_clkctrl inst clkctrl1|ena_register_mode The value assigned is double register and the valid value list is none|falling edge" (WARNING)

SHould I be worried about this, if so what do i do about it?

thanks again

D