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Lorne_K_Intel's avatar
Lorne_K_Intel
Icon for New Contributor rankNew Contributor
5 years ago
Solved

Platform Designer HDL generation errors on AN 830: Intel FPGA Triple-Speed Ethernet and On-Board PHY

platform designer qsys_top.qsys generate HDL exited with errors https://fpgacloud.intel.com/devstore/platform/19.3.0/Pro/an-830-intel-fpga-triple-speed-ethernet-and-on-board-phy-chip-reference-desi...
  • SengKok_L_Intel's avatar
    SengKok_L_Intel
    5 years ago

    Hi,

    I found a workaround of this problem, please unzip the attached file to get the two missing folders (crc32 & User_Logic), and then locate it at "platform" folder. After that, you should be able to generate the platform designer of this example.

    Regards -SK

SengKok_L_Intel's avatar
SengKok_L_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

For the permanent fix, we are in progress to update the PAR file in design store, and it may take some time.


Regards -SK