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Lorne_K_Intel's avatar
Lorne_K_Intel
Icon for New Contributor rankNew Contributor
5 years ago
Solved

Platform Designer HDL generation errors on AN 830: Intel FPGA Triple-Speed Ethernet and On-Board PHY

platform designer qsys_top.qsys generate HDL exited with errors https://fpgacloud.intel.com/devstore/platform/19.3.0/Pro/an-830-intel-fpga-triple-speed-ethernet-and-on-board-phy-chip-reference-desi...
  • SengKok_L_Intel's avatar
    SengKok_L_Intel
    5 years ago

    Hi,

    I found a workaround of this problem, please unzip the attached file to get the two missing folders (crc32 & User_Logic), and then locate it at "platform" folder. After that, you should be able to generate the platform designer of this example.

    Regards -SK

SengKok_L_Intel's avatar
SengKok_L_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

hi,


Thank you for letting us know this problem, and I can observe the same error from my site.


It look like the hw.tcl files for those customer components in this design was not included in the par file. I will contact the owner of this design to obtain those missing files. Will keep you updated.


Regards -SK


SengKok_L_Intel's avatar
SengKok_L_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi,

I found a workaround of this problem, please unzip the attached file to get the two missing folders (crc32 & User_Logic), and then locate it at "platform" folder. After that, you should be able to generate the platform designer of this example.

Regards -SK

  • Lorne_K_Intel's avatar
    Lorne_K_Intel
    Icon for New Contributor rankNew Contributor
    5 years ago

    Thanks, SengKok.
    The solution works perfectly.