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EMOEN's avatar
EMOEN
Icon for New Contributor rankNew Contributor
5 years ago

PCS bonding channels must be locked in ascendning and continous order.

Hi, I am currently trying to compile the "Intel FPGA HDMI IP" for an Achilles Arria 10 Instant Dev kit. I am using the Inrevium HDMI 2.0 FMC card. After filling in the pinout i get the following er...
Deshi_Intel's avatar
Deshi_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi Espsea,

Your location pin placement looks fine. Attached is HDMI example design pin placement for another Arria 10 GX FPGA. You can see the HDMI pin placement is more or less alike.

Maybe you can try double check again the following

  • make sure you select the correct Arria 10 FPGA device part number in Quartus project
  • Ensure nothing wrong with your Quartus project pin assignment setting, HDMI RX channel is configured correctly as well
  • Ensure transceiver refclk is using same refclk from same transcevier bank if possible

Feel free to also generate HDMI example design from Intel FPGA HDMI IP to cross check the pin setting with your project.

If you still can't find the fitter problem, then feel free to archived your Quartus project into *.qar file and share with me. Let me know which Quartus version that you used then I can help to review your design HDMI pin setting as well.

Thanks.

Regards,

dlim