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EMOEN's avatar
EMOEN
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6 years ago

PCS bonding channels must be locked in ascendning and continous order.

Hi, I am currently trying to compile the "Intel FPGA HDMI IP" for an Achilles Arria 10 Instant Dev kit. I am using the Inrevium HDMI 2.0 FMC card. After filling in the pinout i get the following er...
EMOEN's avatar
EMOEN
Icon for New Contributor rankNew Contributor
6 years ago

Hi,

Thank you for the reply!

I am using the following pinout which corresponds to the following

transceiver channels (according to manual from ReflexCES):

fmcb_dp_c2m_p[0] -> PIN_F32 -> Transceiver TX bank 1F lane 3

fmcb_dp_c2m_p[1] -> PIN_H32 -> Transceiver TX bank 1F lane 2

fmcb_dp_c2m_p[2] -> PIN_C34 -> Transceiver TX bank 1F lane 1

fmcb_dp_c2m_p[3] -> PIN_E34 -> Transceiver TX bank 1F lane 0

It does look like the channels are in a continous order in the Tranceiver TX 1F bank.

Regards,

Espsea