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EMOEN's avatar
EMOEN
Icon for New Contributor rankNew Contributor
6 years ago

PCS bonding channels must be locked in ascendning and continous order.

Hi, I am currently trying to compile the "Intel FPGA HDMI IP" for an Achilles Arria 10 Instant Dev kit. I am using the Inrevium HDMI 2.0 FMC card. After filling in the pinout i get the following er...
Deshi_Intel's avatar
Deshi_Intel
Icon for Regular Contributor rankRegular Contributor
6 years ago

Hi,

Arria 10 Transcevier (XCVR) bank typically has 6 channel [5:0] in a bank.

PCS bonding channels must be locked in ascending and continuous order

  • means that all the 4 HDMI channels must be stick together side by side without a gap in between the channels
  • ok example : assign 4 HDMI channels = XCVR [3:0]
  • ok example : assign 4 HDMI channels = XCVR [5:2]
  • not ok example : assign 4 HDMI channels = XCVR [4:2] + XCVR [0]

I hope I clear your doubt

Thanks.

Regards,

dlim