pciex4 ip core on cyclone iv gx F27

Hello, I know I'm quite late to the rest of the posts, but I had the same problem and have solved it.

The problem is the assignment of the reference clock and the PLL clock:

-The reference clock is used for calibration (cal_blk_clk)

-The PLL clock is used to generate the transceiver main clock (pll_inclk)

these two clock may not be from the same source!

Even if the frequencies are appropriate for both clock inputs, they come from different sources! The reference clock has its own dedicated refclk pin. Please make sure you use only this pin for the cal_blk_clk. Make sure you use this pin for nothing else! The error message should be more informative, but if you read about the transceiver architecture of your device you will understand why these two clocks must come from separate sources.

Even if you leave the software to automatically select pin locations, your schematic/HDL must not have these two clock inputs come from the same source. There is nothing the fitter can do if you have them originate from the same source since the design is impossible to fit.