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Honored Contributor
Honored Contributorpciex4 ip core on cyclone iv gx F27
I have designed and data acquisition card. it uses pcie x4 interface to communacate with the host computer. the card is base on an cyclone iv gx 50 F672 fpga device, the quartus ii software ve...
Altera_ForumHonored Contributor
Honored Contributorfrom the attachment picture:
I can see that the successful compilation pcie ip core uses the refclk2 clock pins, the pcie refclk inputs to the pll_1. the failed compilation pcie ip core uses the refclk0 clock pins, the pcie refclk inputs to the pll_5. the two verisions are different from the pll_1 and pll_5. the default pcie core uses the pll_1. but i want to use the pll_5. how can i do this?
